1. Field of the Invention
The present invention relates to a split gate-type nonvolatile semiconductor memory device and a method of manufacturing the same. In particular, the present invention relates to a split gate-type nonvolatile semiconductor memory device provided with an erase gate and a method of manufacturing the same.
2. Description of Related Art
Flash memories and EEPROMs are known as electrically erasable/programmable nonvolatile semiconductor memory devices. A memory cell of such a nonvolatile semiconductor memory device is typically a transistor provided with a floating gate and a control gate. The control gate may be stacked on the floating gate or may be formed on at least a channel region lateral to the floating gate. The latter one is generally referred to as a “split gate-type”, which is excellent in terms of prevention of over-erasure and improvement in read speed.
Typical data programming/erasing methods with respect to the above-mentioned memory cell are as follows. The data programming is achieved by a CHE (Channel Hot Electron) method. More specifically, appropriate program potentials are respectively applied to the control gate and a drain, and thereby hot electrons generated in the vicinity of the drain are injected into the floating gate. On the other hand, the data erasing is achieved by an FN (Fowler-Nordheim) tunneling method. More specifically, a high potential is applied to the control gate, and electrons in the floating gate are extracted to the control gate through a tunnel insulating film due to the FN tunneling.
Here, the following problem can arise. In the case of the above-mentioned split gate-type, the control gate is formed on the channel region through a gate insulating film. Meanwhile, it is necessary at the time of data erasing to apply a high potential to the control gate in order to achieve the FN tunneling as mentioned above. Therefore, the gate insulating film immediately under the control gate to which the high potential is applied cannot be made thin, from a viewpoint of reliability. When the gate insulating film between the control gate and the channel region cannot be made thin, a read current at the time of data reading is reduced and thus the read speed is decreased.
As a technique proposed for solving such a problem, an “erase gate” for use in the data erasing is provided separately from the control gate (refer to Japanese Laid-Open Patent Application JP-2001-230330, Japanese Laid-Open Patent Application JP-2000-286348, Japanese Laid-Open Patent Application JP-2001-85543). At the time of data erasing, a high potential is applied not to the control gate but to the erase gate. As a result, electrons in the floating gate are extracted to the erase gate due to the FN tunneling. Since there is no need to apply a high potential to the control gate at the time of data erasing, it becomes possible to make the gate insulating film immediately under the control gate thin. Consequently, the decrease in the read speed can be prevented.
FIG. 1 shows a memory cell disclosed in Japanese Laid-Open Patent Application JP-2001-230330. A device isolation film 72 is formed on a silicon substrate 60 by a LOCOS (Local Oxidation of Silicon) method. A floating gate 64 is formed on the silicon substrate 60 through a gate oxide film 63. A selective oxide film 66 is formed on the floating gate 64 by a selective oxidation method. The selective oxide film 66 is made thick at the center of the floating gate 64, and consequently an upper surface of the floating gate 64 has a dent. Moreover, a tunnel oxide film 67 is so formed as to cover the device isolation film 72, side surfaces of the floating gate 64, and the selective oxide film 66. An erase gate 68 is formed on the tunnel oxide film 67, and an oxide film 69 is formed on the erase gate 68. As shown in FIG. 1, the erase gate 68 faces the upper surface of the floating gate 64 across the selective oxide film 66 and the tunnel oxide film 67, and further faces the side surfaces of the floating gate 64 across the tunnel oxide film 67. The side surfaces of the floating gate 64 are vertical.
FIG. 2 shows a memory cell disclosed in Japanese Laid-Open Patent Application JP-2000-286348. A source region 81 and a drain region 82 are formed in a silicon substrate 80. A floating gate 84 and a control gate 85 are formed on the silicon substrate 80 through a gate oxide film 83. Furthermore, an erase gate 86 is formed on the source region 81 through the gate oxide film 83 and a tunnel oxide film 87. The tunnel oxide film 87 is also formed between the floating gate 84 and the erase gate 86, and an oxide film 88 is formed between the floating gate 84 and the control gate 85. Silicide films 89, 90 and 91 are formed on upper surfaces of the drain region 82, the control gate 85 and the erase gate 86, respectively. As shown in FIG. 2, the erase gate 86, which is formed over the source region 81, faces a part of a upper surface and the whole of side surfaces of the floating gate 84 across the tunnel oxide film 87. The side surfaces of the floating gate 84 are vertical.
FIG. 3 shows a memory cell disclosed in Japanese Laid-Open Patent Application JP-2001-85543. A source region 101 and a drain region 102 are formed in a silicon substrate 100. A control gate 105 and a floating gate 106 are formed on a channel region through gate insulating films 103 and 104, respectively. An oxide film 109 is formed on the control gate 105. A source interconnection 110 is formed on the source region 101. Furthermore, a tunnel oxide film 108 is so formed as to cover the floating gate 106, the oxide film 109 and the source interconnection 110. An erase gate 107 is formed on the tunnel oxide film 108. As shown in FIG. 3, the floating gate 106 has a first side surface that is vertical and a second side surface that is curved. The first side surface and the second side surface are connected with each other at a top edge portion of the floating gate 106, and an interval between the first side surface and the second side surface becomes larger from the top edge portion towards the silicon substrate 100. In other words, the floating gate 106 is sharp towards the top edge portion. The erase gate 107 faces the top edge portion of the floating gate 106 across the tunnel oxide film 108.
The inventor of the present application has recognized the following points. In order to improve an erase efficiency, an electric field concentration at an acute-angled portion of the floating gate facing the erase gate may be utilized. The inventor has considered that the acute-angle portion of the floating gate facing the erase gate can be formed by incurving both side surfaces of the floating gate. Such a floating gate whose both side surfaces are incurved can be fabricated as follows for example.
As shown in FIG. 50, a gate insulating film 2 is formed on a semiconductor substrate 1, and device isolation structures 6-1 and 6-2 projecting from the semiconductor substrate 1 are formed. The device isolation structure 6-1 has a first projecting portion PR1 that projects from the semiconductor substrate 1, and the device isolation structure 6-2 has a second projecting portion PR2 that projects from the semiconductor substrate 1. By removing respective upper edge portions of the first projecting portion PR1 and the second projecting portion PR2 through an etching, a first sloping surface SLP1 and a second sloping surface SLP2 are respectively formed on the first projecting portion PR1 and the second projecting portion PR2, as shown in FIG. 50. The first sloping surface SLP1 and the second sloping surface SLP2 face each other, and an interval between the first sloping surface SLP1 and the second sloping surface SLP2 becomes larger away from the semiconductor substrate 1. Then, a floating gate is so formed as to be sandwiched between the first projecting portion PR1 and the second projecting portion PR2. Since both side surfaces of the floating gate thus formed are respectively in contact with the first sloping surface SLP1 and the second sloping surface SLP2, the both side surfaces are incurved.
However, in the case where the first sloping surface SLP1 and the second sloping surface SLP2 are formed by the etching, the following problem can arise. That is, if the upper edge portions of the first projecting portion PR1 and the second projecting portion PR2 are over-etched, the semiconductor substrate 1 is exposed as shown in FIG. 50 and a so-called “divot” occurs. The divot remarkably deteriorates reliability of the device. In order to secure the reliability of the device, it is desirable to suitably form the acute-angled portion of the floating gate without generating the divot.